1. Field of the Invention
The present invention relates to improvements of an integrated injection logic circuit.
2. Description of the Prior Art
A conventional integrated injection logic circuit (hereinafter simply referred to as I.sup.2 L circuit ) will hereinafter be described with reference to FIG. 1. In FIG. 1, reference numeral 6 generally designates an I.sup.2 L circuit wherein reference numerals 1 and 2 respectively designate input and output terminals thereof. Reference characters Q11 and Q12 respectively designate constant current source transistors of PNP type and Q21 and Q22 switching inverter transistors of NPN type. The emitters of the transistors Q11 and Q12 are connected together to an injector IJ and the injector IJ is connected through a resistor 3 to a voltage source +B (for example, +5 V). The collectors of the transistors Q11 and Q12 are respectively connected to the bases of the transistors Q21 and Q22, and the collector of the transistor Q21 is connected to the base of the transistor Q22. The emitters of the transistors Q21 and Q22 and the bases of the transistors Q11 and Q12 are all connected to a wall WL and the wall WL is grounded. In general, a unit circuit formed of a constant current source transistor and a switching inverter transistor supplied at its base with the constant current from the constant current source transistor can arbitrarily be connected in cascade between the injector IJ and the wall WL.
Further, an NPN transistor Q20 is provided the collector of which is connected to the base of the transistor Q21. The emitter thereof is connected to the wall WL and from the base of which is led out the input terminal 1. The output terminal 2 is led out from the collector of the transistor Q22.
Reference numeral 4 designates an output terminal of a circuit to be connected to the I.sup.2 L circuit 6 at its input side. This output terminal 4 is connected through an interface circuit 5 to the input terminal 1 of the I.sup.2 L circuit 6.
The logic high level and the logic low level developed at the output terminal 2 of such I.sup.2 L circuit 6 are respectively about 0.7 V and 0 V. Accordingly, when the logic high level and the logic low level of the output developed at the output terminal 4 of the circuit (for example, TTL (transistor-transistor logic) circuit) to be connected to the input side of the I.sup.2 L circuit 6 are respectively 4 V and 1 V, since the withstanding voltage of the I.sup.2 L circuit 6 is approximately 1.4 V, the input interface circuit 5 connected therebetween must have a quite complicated structure.
An example of the 3-bit D/A (digital-to-analog) converter using such I.sup.2 L circuit as a gate circuit will be described with reference to FIG. 2. Reference numerals 11, 12 and 13 respectively designate input terminals of 3-bit digital signals, and the 3-bit digital signals are respectively supplied therefrom to gate circuits 14, 15 and 16, each of which is formed of the I.sup.2 L circuit. Reference numerals Q31, Q32 and Q33 respectively designate first constant current source transistors of PNP type and the transistors Q32 and Q33 are made as multi-transistors. The ratio of the collector currents of the transistors Q31, Q32 and Q33 is selected as 1:2:4. The emitters of the transistors Q31, Q32 and Q33 are respectively connected through an injector IJ and a resistor 17 to the voltage source +B. Reference numerals Q41, Q42 and Q43 respectively designate second constant current source transistors of PNP type, and the transistors Q42 and Q43 are made as multi-transistors. The ratio of the collector currents of the transistors Q41, Q42 and Q43 is selected also as 1:2:4, and the emitters of the transistors Q41, Q42 and Q43 are respectively connected to the collectors of the transistors Q31, Q32 and Q33 and the collectors of the transistors Q41, Q42 and Q43 are connected together. The bases of the transistors Q31 to Q33 and Q41 to Q43 are respectively connected to the wall WL and the wall WL is grounded through a diode 18.
Reference numeral 19 designates a current to voltage converting circuit. The collectors of the transistors Q41 to Q43 are connected together to a base of an NPN transistor 20 in the circuit 19 and the base of the transistor 20 is grounded through a diode 21. The emitter of the transistor 20 is grounded and the collector thereof is connected through a load resistor 22 to the voltage source +B and connected to an output terminal 23.
This D/A converter requires the current to voltage converting circuit 19 because the above I.sup.2 L circuit shown in FIG. 1 is used as the gate circuits 14 to 16 thereof. As a result, the non-linear factor such as Early effect or the like of the output transistor 20 is added to the output of the D/A converter, thus obstructing the characteristic of the D/A converter from being improved.